Compact High Performance Algorithm for Convolutional Decoder

Authors

  • Arsen Hakhoumian nstitute of Radiophysics and Electronics, Armenian National Ac.Sci.
  • Tigran Zakaryan Institute of Radiophysics and Electronics, Armenian National Ac.Sci.
  • Aramazd Muzhikyan Institute of Radiophysics and Electronics, Armenian National Ac.Sci.
  • Vahan Nikoghosyan Institute of Radiophysics and Electronics, Armenian National Ac.Sci.

Abstract

An efficient algorithm for convolutional decoder running in the mode of soft decision (1/2, K=7, 3-bit decision) in a FPGA Virtex-II is proposed. The results show that although increasing the length of the cutoff buffer improves the signal to noise ratio by 2dB, but it can significantly increase calculation time, which exponentially depends on the length of the cutoff buffer. At the optimal length of the cutoff buffer equal to 7, the obtained throughput is estimated up to 14Mbps.

References

M Hosemann. R.Habendorf and G.Fettweis, “Hardware-software codesign of A 14.4mbit - 64 State viterbi decoder for an application-apecific digital signal processor”, IEEE Workshop on Signal Processing Systems, pp. 45-50, 2003.

M.Röder and R.Hamzaoui, “Fast tree-trellis list viterbi decoding”, IEEE Transactions on Communications, vol. 54, no. 3, pp. 453-461, 2006

J.Campos and R.Cumplido, “A runtime reconfigurable architecture for viterbi decoding”, 3rd International Conference on Electrical and Electronics Engineering , pp. 1-4, 2006.

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Published

2021-12-10

How to Cite

Hakhoumian, A. ., Zakaryan, T. ., Muzhikyan, A. ., & Nikoghosyan, V. . (2021). Compact High Performance Algorithm for Convolutional Decoder. Mathematical Problems of Computer Science, 35, 137–139. Retrieved from http://93.187.165.2/index.php/mpcs/article/view/296

Issue

Vol. 35 (2011): Mathematical Problems of Computer Science

Section

Articles

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